Clock Gating Aware Low Power ALU Design and Implementation on FPGA

In this paper the authors deal with the design and implementation of a clock gating aware low power arithmetic and logic unit that has been developed as part of low power processor design in the platform Xilinx ISE 14.2 and synthesized on 90nm Spartan-3 FPGA. Clock power contributes 45-60 percent of total dynamic power. Hence, clock power reduction is necessary in low power design. In this paper, they analyze theoretical 93.75% clock power reduction in ALU using clock gating techniques.

Provided by: International Association of Computer Science & Information Technology (IACSIT) Topic: Hardware Date Added: Oct 2013 Format: PDF

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