Clock Gating for Dynamic Power Reduction in Synchronous Circuits

Provided by: International Journal of Engineering Trends and Technology
Topic: Hardware
Format: PDF
In this paper, clock gating technique is presented for low power VLSI (Very Large Scale Integration) circuit design. Clock in digital circuits is used for synchronization of various components. Clock power is a major source of dynamic power consumed in synchronous circuits. Clock gating is a well-known technique to reduce clock power. In clock gating clock to an idle block is disabled. Thus, significant amount of power consumption is reduced by employing clock gating. In this paper, a 4-bit synchronous counter is designed using clock gating.

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