Clock-Less Design Methodology for Digital System Design

Provided by: International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE)
Topic: Hardware
Format: PDF
As design systems have grown in complexity and clock speeds are constantly increasing, several limitations to the conceptual framework of synchronous design have begun to be noticed. Some notable problems due to higher performance demand are difficulty in global distribution of clock, clock skew, high power dissipation, interfacing difficulties and traversing the chips longest wire in one clock cycle. It is therefore not a surprise that the area of asynchronous circuits and systems, which generally do not suffer from these problems are gaining importance.

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