The design of body driven quaternary logic generator is based on CMOS circuit in which pMOS and nMOS are connected drain to drain and their gates are common and driven by a bias potential. This paper is about the design, simulation and study of a CMOS quaternary logic generator having a single stage CMOS body driven design. The interest of design is that the circuit consists of only one CMOS circuit, reducing the chip area and also only two supply rails is required to drive the complete circuitry. The multi-valued logic generator, designed here is also demonstrated with and without enable circuitry too. The design has been implemented with 1.8micrometer CMOS technology on Cadence virtuoso schematic Editor.