CMOS Circuit Layout Design for Sub Threshold Leakage Power Optimization

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Provided by: IJAIM
Topic: Hardware
Format: PDF
The recent reduction in transistor size using scaling will cause sub-threshold leakage currents to become an increasingly large component of total power dissipation. In this paper, a stack transistor technique using two series connected stack is use to design the digital circuit. The total leakage current is the function of inputs, thus the authors model the leakage current for each input states. The static and dynamic power of stack is considerably low. But, it has a delay penalty and its area requirement is maximum compared with other processes.
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