CMOS Design of Area and Power Efficient Multiplexer using Tree Topology
In this paper, a design of 16:1 tree type multiplexer has been presented using GDI and PTL technique. The proposed design consists of 31 NMOS and 15 PMOS. The proposed multiplexer is designed and simulated using DSCH 3.1 and MICROWIND 3.1 on 180nm technology. Performance comparison of proposed multiplexer with CMOS, pass transistor and transmission gate logic design techniques is also presented. The different logics are compared with respect to area and power. A power comparison with respect to supply voltage has been performed using 180nm technology.