CMOS Layout Design and Performance Analysis for Synchronization Failures Using 50nm Technology

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Provided by: International Journal of Computer Applications
Topic: Hardware
Format: PDF
The synchronizer is constrained such that its state does not change when a latching operation fails. Therefore, any failed latching attempts are automatically retried in the subsequent cycles. For this, the authors simulates the 8-bit multiplier, 4-bit 16 state finite state machine, 16 slot 8-bit data first in first out register, etc. In a multi-clock system, synchronizers are required when on-chip data cross the clock domain boundaries which guard against synchronization failures but introduce latency in processing the asynchronous input.
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