Co-optimisation of Datapath and Memory in Outer Loop Pipelining

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Provided by: Imperial College London
Topic: Hardware
Format: PDF
When targeting algorithms to FPGAs both the array to memory assignment and the selection of data reuse structures should be considered to maximize performance. In this paper the authors present an Integer Linear Programming formulation for the combined problem of array to memory assignment and data reuse selection. They include a number of cost functions to minimize during memory optimization and show how these optimizations can be integrated into a loop pipelining framework to iteratively update the memory subsystem during scheduling.
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