Institute of Electrical & Electronic Engineers
Reconfigurable computing is a technology that aims to combine the performance of FPGAs with the programmability/flexibility found in General Purpose Processors (GPPs) in a unified and easy programming environment. This paper presents a code compression and on-the-fly decompression scheme suitable for coarse-grain reconfigurable technologies. A novel unit-grouping dictionary based compression technique utilizing special control bits to increase the effective storage capacity of the dictionaries is implemented and compared against an existing suitable technique for an example reconfigurable system. Compressions ratios in the range of 40%-59% are recorded with new scheme.