International journal of Engineering and Management Research (IJEMR)
Highly-increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using Dominos CMOS logic style.