Combining Data Reuse With Data-Level Parallelization for FPGA Targeted Hardware Compilation: A Geometric Programming Framework
A non-linear optimization framework is proposed in this paper to automate exploration of the design space consisting of data reuse (buffering) decisions and loop-level parallelization, in the context of FPGA-targeted hardware compilation. Buffering frequently accessed data in on-chip memories can reduce off-chip memory accesses and open avenues for parallelization. However, the exploitation of both data reuse and parallelization is limited by the memory resources available on-chip. As a result, considering these two problems separately, e.g. first exploring data reuse and then exploring data-level parallelization, based on the data reuse options determined in the first step, may not yield the performance-optimal designs for limited on-chip memory resources.