Comparative Analysis of DES and S-DES Encryption Algorithm Using Verilog Coding
In this paper, the authors present a comparative analysis of data encryption standard and simplified data encryption standard algorithm and compare the result of DES and SDES encryption for improve the algorithm performance. The Xilinx Tool is used to synthesize DES and simplified DES algorithm. The performance in terms of delay, power and area of DES and Simplified DES analyzed using Cadence Encounter RTL compiler. The design analysis of simplified DES shows leakage power is 568nW and transition power is 169186.883nW, so the total power is 169755.035nW, the delay is 3422ps and dies area 1468μm2 on 130nm process technology.