International Journal of Engineering Research and Development (IJERD)
As the integration density and complexity of the System-On-Chip (SOC) increases, the conventional interconnects are not suitable to fulfill the demands. The application of traditional network technologies in the form of Network-on-Chip is a possible solution. NoC design space has numerous variables. As an improved topology is selected complexities decrease and power-efficiency increases. In this paper, the main research field in Network-on-chip design focusing on optimized topology design is analyzed. The simulation is modeled using a conventional network simulator tool ns-2, in which by selecting proposed Topology 35.7 % reduction in traversing the longest path is observed.