International Journal of Emerging Technology in Computer Science and Electronics ( IJETCSE)
An adder is a basic component in a central processing unit. A carry look-ahead adder improves speed by reducing the amount of time required to resolve the carry bits. In this paper, 4-bit CLA has been designed using various logic styles such as Standard CMOS, DCVS, Pseudo NMOS, PTL and Domino logic style. Performance of CLA is measured by comparing the results in terms of propagation delay, power dissipation and power delay product. The paper also includes the design of a modified carry look-ahead adder which based on the analysis can be regarded faster the carry look-ahead adder.