International Journal of Computer Applications
Design and simulation of conventional CMOS full adder using 45nm technology at specified node has been presented here. This research paper shows comparison about post layout simulations of designed low power CMOS full adder. It also explains about performance analysis of optimized low power CMOS full adder at different loads. This design has achieved 63.11nW active power consumption with propagation delay of 0.254ns and having leakage current of 0.798nA at the supply voltage of 0.7V. Cadence's virtuoso tool has been used for circuit design.