A SRAM cell must meet requirements for operation in submicron/ nano ranges. The scaling of CMOS technology has significant impact on SRAM cell – random fluctuation of electrical characteristics and substantial leakage current. In this paper, the authors present dynamic column based power supply 8T SRAM cell and comparing the proposed SRAM cell with respect to conventional SRAM 6T in respect to power and delay on various CMOS technology. Simulation results affirmed that proposed 8T SRAM cell consumes less power as compare to basic 6T SRAM cell with improved read stability, read current, and leakage current on different technologies.