Multiple Valued Logic (MVL) has some important benefits such as increased data density, increased computational ability, reduced dynamic power dissipation Therefore with the help of Multiple Valued Logic (MVL) the authors have designed two quaternary multiplier architecture. The partial products in the multiplier are designed with quaternary voltage mode circuits. Each multiplier architectures are designed with two methods. The performance of two quaternary multiplier architectures is then compared based on Energy Delay Product (EDP) & Power Delay Product (PDP).