The International Journals of Engineering & Sciences (IJENS)
The design of on chip interconnection architecture (NoC) should carefully take on consideration both hardware and communication constraints in order to build up a system that meets quality of service requirements. In the NoC (Network on Chip) architecture, the on chip switch available hardware and software resources drive up the global performances of the communication processes. Therefore it is crucial, before the physical design process, to carry out the required capacities such as buffer depth and management-tasks of a flit. In fact, one of the most critical parameters that can affect communication characteristics are the available memory space in addition to flit-time processing according to a given scheduling approach.