Institute of Research Engineers and Doctors
In this paper, the authors present a comparative study of different redundant binary full adders (Plus-Plus-Minus (PPM) adder). These PPM adders are simulated to evaluate their performance in total power dissipation, speed and PDP. The performances of these circuits are based on 180nm process model at a supply voltage of 1.8V. They also proposed a new design for PPM adder using 13-transistors. The simulation results reveal that the proposed design is more power, area efficient and faster than the best available PPM circuit in the literature.