International Journal of Engineering Development and Research (IJEDR)
In this paper, the authors present the realization of full adder designs using complimentary CMOS design, Complimentary Pass-transistor Logic (CPL) design and XOR-XNOR design in a single unit. This paper is to determine the comparative study of power, delay, Power Delay Product (PDP) of different Full adder designs using CMOS logic styles. Simulations results clearly determines that XOR-XNOR type full adder design is better compared to complimentary CMOS style and pass transistor design with respect to power, delay. power delay product comparison. The power delay product is also important parameter to determines the performance of the design.