Provided by: International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)
Date Added: Aug 2014
The main building block of many arithmetic systems is the adder cells. The performance of multipliers is greatly influenced by the efficiency of the adders. Adder cells using different logic styles are discussed in this paper. Different logic styles include CMOS logic, pass transistor logic, transmission gates and Shannon based adders. This paper is to compare the performance of adder cells in terms of delay, power consumption, area and energy delay product. The adder cells are designed for 0.18um CMOS technology. Cadence tool is used for the simulation.