Provided by: Institute of Electrical & Electronic Engineers
In this paper, the authors present a variability resilient FinFET based 10T SRAM cell. Critical design metrics of SRAM cells are estimated at subthreshold region and compared with that of conventional MOSFET based 10T SRAM cell. The FinFET based SRAM cell offers 2.33× and 1.29× improvements in Read Access Time (TRA) and Write Access Time (TWA) respectively. The proposed bitcell also offers 7.06× and 1.54× improvements in TRA and TWA variability respectively compared to its MOSFET counterpart. Moreover, their bitcell exhibits 20% higher Read Static Noise Margin (RSNM) at a cost of 5% reduction in write static noise margin @ 400 mV.