International Journal of Engineering Research and Applications (IJERA)
In this paper, the authors have provided a method for designing a two stage CMOS operational amplifier which operates at 1.8V power supply using Cadence Virtuoso 45nm CMOS technology. Further, designing the two stage op-amp for the same power supply using Cadence Virtuoso 180nm CMOS technology, keeping the slew rate of the op-amp same as that 45nm technology. The trade-off curves are computed between various characteristics such as gain, phase margin, GBW, 3db gain etc. and the results obtained for 45n CMOS technology is compared with those obtained for 180nm CMOS technology.