Comparative Study of Delay and Power Dissipation of a Low Power CMOS BPSK Modulator Circuit
In this paper the authors have presented a BPSK modulator using low power CMOS technology. The key design issues in VLSI circuit design are power and delay. Thus in this paper they have focused on LP CMOS with different technologies(16nm, 22nm,32nm and 45nm) with the help of TANNER EDA tool. The value of model parameters are used from Predictive Technology Model (PTM). The T-SPICE simulation results indicate that there is a 59% deduction in dynamic power for 16nm technology compare to 45nm technology keeping supply voltage constant whereas there is 74.64% reduction in power delay product in 16nm technology compare to 45nm technology.