International Journal of Engineering Research and Applications (IJERA)
In this paper, the authors present a comparative study of 1-dimensional bypassing multipliers on basis of delay, area and power. If they can reduce the power consumption of the multiplier block, then they can reduce the power consumption of various digital signal processing chips and communication systems. In 2-dimensional bypass multiplier is presented the effective analysis of slices, lut, cost and area is achieved. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL using Xilinx 12.4 ISE. Results are showed and it is verified using the Spartan-3E and Synopsys respectively.