Today’s LDO (Low Drop-Out voltage regulator) must meet the requirements of various future demands of the portable electronics. To get a new approach towards a design of low drop-out voltage regulator that provides a modern System-on-Chip (SoC) solution and fulfils the present commercial requirements as well as the projected demands of the future, it becomes necessary to study the literature work. The various performance matrices such as minimization of drop-out voltage, low power, low operating voltages, low quiescent currents, fast transient response, high PSR and high packing density have a vital importance in designing of LDO regulator.