Comparison of 1 Bit Low Power-High Speed Designs Leakage Minimization Full Adder

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Provided by: International Journal of Advanced Research in Computer Science and Software Engineering (IJARCSSE)
Topic: Hardware
Format: PDF
Low power design has become one of the primary focus in Deep Sub-Micron technology (DSM). Optimization of speed, power & area can be achieved by using Gated Diffusion Input (GDI) technique. In paper a 11T based Adder with 8 & 16 input using GDI technique is proposed and it compared with various existing adder circuit for Average power, delay, Power Delay Product (PDP). Simulations are performed by using Cadence Virtuoso based on 180nm CMOS technology. Area has been evaluated by Microwind using TSMC BSIM 0.120µm technologies.
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