International Journal of Research in Advent Technology (IJRAT)
In this paper, the authors discuss about comparison of the four 24X24 bit unsigned multipliers are done for the various performance parameters. The multipliers included in this comparison are array multiplier, radix 4 booth multiplier, wallace tree multiplier and Vedic multiplier. All multiplier designs were modeled in Verilog HDL and synthesized based on the TSMC 180nm standard cell library. Comparisons are based on the synthesis result obtained by synthesizing all the multiplier using Cadence RTL compiler ultra.