Comparison of IEEE-754 Standard Single Precision Floating Point Multiplier's

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Provided by: Institute of Research in Engineering and Technology (IRET)
Topic: Hardware
Format: PDF
Multipliers are key components of many high performance systems such as FIR filters, microprocessors, digital signal processors, etc. Multiplication based operations such as Multiply and ACcumulate (MAC) and inner product are among some of the frequently used computation-intensive arithmetic functions currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform (FFT), filtering and in microprocessors in its arithmetic and logic unit. An architecture for a fast 32-bit floating point multiplier using array multiplier and Radix-8 Booth's recoding algorithm with the single precision IEEE 754-2008 standard has been presented in this paper. Verilog is used to implement a technology-independent design. Floating point multiplier is synthesized and targeted for Xilinx Spartan-3E FPGA.
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