In present world VLSI technology energy consumption is an important factor to be considered among other factors like area occupation, performance and speed of the portable devices. The reduction in size and complexity of the portable devices have resulted in very large amount of power wastage in the devices. Due to this pneumonia low power VLSI designs have become very important part of portable devices. There is more strategy for designing the lower power VLSI. In this paper, the authors have compared only 2 methods of designing the lower power VLSI using clocked logic style and non-clocked logic style.