Compiler Assisted Dynamic Management of Registers for Network Processors

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encountering long latency memory accesses and this way the parallelism and memory access can be overlapped. Context switches in the typical network processor architectures such as the IXP are designed to be very fast. However, the low overhead is partly achieved by leaving register management to programs, with minimal support from the hardware.
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