Compiling CHR to Parallel Hardware

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
In this paper, the authors investigate the compilation of a committed-choice rule-based language, Constraint Handling Rules (CHR), to specialized hardware circuits. The developed hardware is able to turn the intrinsic concurrency of the language into parallelism. Rules are applied by a custom executor that handles constraints according to the best degree of parallelism the implemented CHR specification can offer. Their framework deploys the target digital circuits through the Field Programmable Gate Array (FPGA) technology, by first compiling the CHR code fragment into a low level hardware description language.
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