Technology is improving in online error detection in Very Large Scale Integration (VLSI). Arithmetic circuits are important blocks in many circuits such as Integrated Circuits (ICs) digital signal processors. Self-checking carry-select adder design based on two-rail encoding is an efficient method, due to its arithmetic operations and short delay. This paper presents the design of the compressor based self-checking carry-select adder design. The circuit can detect all single stuck-at faults during online operation mode. Its performance is increased by using compressor by replacing all full adders.