Concurrent Core Test for SOC Using Shared Test Set and Scan Chain Disable

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Provided by: edaa
Topic: Hardware
Format: PDF
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. Prior to test, the test sets corresponding to Cores Under Test (CUT) are merged by using the proposed merging algorithm to obtain a shared test set with minimum size. During test, the on-chip Scan Chain Disable Signal (SCDS) generator is employed to retrieve the original test vectors from the shared test set. The approach is non-intrusive and Automatic Test Pattern Generator (ATPG) independent. Moreover, the approach can reduce test cost further by combining with general test compression/decompression technique.
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