Concurrently Optimizing FPGA Architecture Parameters and Transistor Sizing: Implications for FPGA Design

Provided by: Imperial College London
Topic: Hardware
Format: PDF
This paper presents a method that combines high-level and low-level architecture parameter exploration. The paper builds on an increasing body of work concerned with modeling reconfigurable architectures, and presents a full area and delay model of an FPGA. The optimization of this model is based on the use of Geometric Programming, and allows high-level architecture parameter selection and transistor sizing to be done concurrently. They use the framework to demonstrate that concurrent optimization of both high and low-level parameters can lead to significantly different architectural conclusions.

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