Delft University of Technology
In this paper the authors present the design and implementation of configurable fault-tolerance techniques for a configurable VLIW processor. The processor can be configured for 2, 4, or 8 issue-slots with different types of execution Functional Units (FUs), and its Instruction Set Architecture (ISA) is based on the VEX ISA. Separate techniques are employed to protect different modules of the processor from Single Event Upsets (SEU) errors. Parity checking is utilized to detect errors in the instruction and data memories and the General Register file (GR), while Triple Modular Redundancy (TMR) approach is employed for all the synchronous Flip-Flops (FFs).