Constant Bit Rate Traffic Investigation for Network-on-Chip
Scalable Networks on Chips (NoCs) are needed to match the ever-increasing communication demands of large-scale Multi-Processor Systems-on-chip (MPSoCs) for high-end wireless communications applications. The heterogeneous nature of on-chip cores, and the performance efficiency requirements typical of high end computing devices call for efficient NoCs architecture which eliminate much of the overheads connected with general-purpose communication architectures. This paper evaluates the performance of regular and Irregular NoC for constant bit rate traffic pattern for various routing algorithms such as X-Y, O-E, Up/down. The performance of NoC with varying number of cores is evaluated on the systemC based discrete event, cycle accurate NoC performance simulator.