Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-on-Chips (MPSoCs), the authors focus on the problem of implementing efficient interconnect systems for devices which are ever more densely packed with parallel computing cores. Easily seen that traditional buses cannot provide enough bandwidth, a revolutionary path to scalability is provided by packet-switched Network-on-Chips (NoCs), while a more conservative approach dictates the addition of bandwidth-rich components (e.g. crossbars) within the preexisting fabrics. While both alternatives have already been explored, a thorough contrastive analysis is still missing.