Control Loop Feedback Mechanism for Generic Array Logic Chip Multiprocessor

Provided by: Cornell University
Topic: Hardware
Format: PDF
Control Loop Feedback Mechanism for Generic Array Logic Chip Multiprocessor is presented. The approach is based on control-loop feedback mechanism to maximize the efficiency on exploiting available resources such as CPU time, operating frequency, etc. Each Processing Element (PE) in the architecture is equipped with a frequency scaling module responsible for tuning the frequency of processors at run-time according to the application requirements. The authors show that generic array logic Chip Multiprocessors with large inter-processor First In First Outputs (First In First Outs) buffers can inherently hide much of the Generic Array Logic performance penalty while executing applications that have been mapped with few communication loops.

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