In embedded Digital Signal Processing (DSP) systems, quality is set by a Signal-to-Noise Ratio (SNR) floor. Conventional digital design strategies guarantee timing correctness of all operations, which leaves large quality margins in practical systems and sacrifices energy efficiency. This paper presents techniques to significantly improve energy efficiency by shaping the quality-energy tradeoff achievable via VDD scaling. In an unoptimized design, such scaling leads to rapid loss of quality due to the onset of timing errors. The authors introduce techniques that modify the behavior of the early and worst timing error offenders to allow for larger VDD reduction.