Convex Optimization of Resource Allocation in Asymmetric and Heterogeneous SoC

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Provided by: Technion - Israel Institute of Technology
Topic: Hardware
Format: PDF
Chip area, power consumption, execution time, off-chip memory bandwidth, overall cache miss rate and Network-on-Chip (NoC) capacity are limiting the scalability of SoCs. Consider a workload comprising a sequential and multiple concurrent tasks and asymmetric or heterogeneous SoC architecture. A convex optimization framework is proposed, for selecting the optimal set of processing cores and allocating area and power resources among them, the NoC and the last level cache, under constrained total area, total average power, total execution time and off-chip bandwidth.
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