Institute of Electrical & Electronic Engineers
Efficient sharing of system resources is critical to obtaining high utilization and enforcing system-level performance objectives on Chip Multi-Processors (CMPs). Although several proposals that address the management of a single micro-architectural resource have been published in the literature, coordinated management of multiple interacting resources on CMPs remains an open problem. The authors propose a framework that manages multiple shared CMP resources in a coordinated fashion to enforce higher-level performance objectives. They formulate global resource allocation as a machine learning problem. At runtime, their resource management scheme monitors the execution of each application, and learns a predictive model of system performance as a function of allocation decisions.