Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed methodology handles both flat bus single processor SOC and hierarchical bus multiprocessor SOC. It is based on a resource graph manipulation and a packet-based packet set scheduling methodology. The resource graph is decomposed into a set of test configuration graphs, which are then used to determine the optimum test configurations and test delivery schedule under a given power constraint.

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