Cost-Effective Scalable QC-LDPC Decoder Designs for Non-Volatile Memory Systems
Non-Volatile Memory Systems (NVMS) have been prevailed among many consumer electronic products, including mobile devices, computers, and the promising Solid-State Drives (SSDs). With the advanced manufacturing technology, the storage density of NVMS, particularly those consist of Multi-Level Cell (MLC) flash memories, grows fast since more bits are able to be accommodated within a cell. This paper presents a cost-effective scalable Quasi-Cyclic LDPC (QC-LDPC) decoder architecture for Non-Volatile Memory Systems (NVMS). A re-arranged architecture is proposed to eliminate the First-In-First-Out (FIFO) memory in conventional decoders, where the FIFO size is linearly proportional to the codeword size.