Cost-Effectively Offering Private Buffers in SoCs and CMPs

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Provided by: Association for Computing Machinery
Topic: Storage
Format: PDF
High performance SoCs and CMPs integrate multiple cores and hardware accelerators such as network interface devices and speech recognition engines. Cores make use of SRAM organized as a cache. Accelerators make use of SRAM as special-purpose storage such as FIFOs, scratchpad memory, or other forms of private buffers. Dedicated private buffers provide benefits such as deterministic access, but are highly area inefficient due to the lower average utilization of the total available storage. The authors propose Buffer-integrated-Caching (BiC), which integrates private buffers and traditional caches into a single shared SRAM block.
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