Cost Model-Driven Test Resource Partitioning for SoCs

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Provided by: University of South Florida
Topic: Hardware
Format: PDF
The main factors contributing to the cost of System-on-Chip (SoC) manufacturing test are the required number of tester pins, the test application time, the tester memory requirements and the area overhead required by the test resources. These factors contribute with different weights, depending on the cost model of each SOC. Several methods have been recently proposed to optimize each of these factors, however none of the existing methods employs an objective function derived from the actual cost model of each product.
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