Counterexample-Guided SMT-Driven Optimal Buffer Sizing

Provided by: edaa
Topic: Hardware
Format: PDF
The quality of Network-on-Chip (NoC) designs depends crucially on the size of buffers in NoC components. While buffers impose a significant area and power overhead, they are essential for ensuring high throughput and low latency. In this paper, the authors present a new approach for minimizing the cumulative buffer size in on-chip networks, so as to meet throughput and latency requirements, given high-level specifications on traffic behavior. Their approach uses model checking based on Satisfiability Modulo Theories (SMT) solvers, within an overall counterexample-guided synthesis loop.

Find By Topic