Institute of Electrical & Electronic Engineers
The authors propose a novel approach to the computation of the CRC functions, commonly used for bit error checking purposes when handling binary data. This approach is designed for general hashing purposes in FPGA, for which the CRCs are usable as well. The method is suitable for applications which use parallel inputs of fixed size and require high throughput, such as hash tables. They employ the DSP blocks present in modern FPGAs to perform all the necessary XOR operations, so that their solution does not consume any LUTs. They propose a Monte Carlo based heuristic to reduce the number of the DSP blocks required by the computation.