Cross-Abstraction Functional Verification and Performance Analysis of Chip Multiprocessor Designs

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
In this paper, the authors introduce the Cross-Abstraction Real-time Analysis (CARTA) framework for the model-based functional verification and performance estimation of Chip Multi-Processors (CMP) utilizing bus matrix (crossbar switch) interconnection networks. They argue that the inherent complexity in CMP designs requires the synergistic use of various models of computation to efficiently manage the trade-offs between accuracy and complexity. Their approach builds on Domain-Specific Modeling Languages (DSMLs) driving an open-source tool-chain that provides a cross-abstraction bridge between the Finite State Machine (FSM), Discrete Event (DE) and Timed Automata (TA) models of computation, and utilizes multiple model checkers to analyze formal properties at the cycle-accurate and transaction-level abstractions.
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