Cross-Layer Optimized Placement and Routing for FPGA Soft Error Mitigation

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Provided by: European Design and Automation Association
Topic: Storage
Format: PDF
As the feature size of FPGA shrinks to nanometers, soft errors increasingly become an important concern for SRAM-based FPGAs. Without consideration of the application level impact, existing reliability-oriented placement and routing approaches analyze Soft Error Rate (SER) only at the physical level, consequently completing the design with suboptimal soft error mitigation. The authors' analysis shows that the statistical variation of the application level factor is significant. Hence in this paper, they propose a cube-based analysis to efficiently and accurately evaluate the application level factor.
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